Hardware Architecture of a Decoder for Fractal Image Compression

Hasanujjaman, U. Biswas, M. Naskar
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Abstract

Fractal image compression is a comparatively new and less explored technique in the domain of image processing. The main problem is it's very high image compression time due to the huge number of ‘range’ - ‘domain’ comparisons it has to undergo. If efficiently utilised, fractal image compression gives the best compression ratio which is highest among other contemporary techniques. In this paper we have proposed efficient hardware of a decoder for the fractal image compression. Controlled parallelism has been incorporated to speed up the decoding process. The whole design has been simulated and synthesized using verilog HDL.
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分形图像压缩解码器的硬件结构
在图像处理领域,分形图像压缩是一种相对较新的、探索较少的技术。主要问题是它的图像压缩时间非常高,因为它必须经历大量的“范围”-“域”比较。如果有效地利用,分形图像压缩给出了最好的压缩比,这是其他当代技术中最高的。本文提出了一种高效的分形图像压缩解码器硬件。控制并行已被纳入,以加快解码过程。利用verilog HDL对整个设计进行了仿真和综合。
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