H. Lo, Jianwei Peng, P. Zhao, E. Bazizi, Yue Hu, Y. Shi, Y. Qi, A. Vinslava, Y. Shen, W. Hong, H. Zang, Xing Zhang, A. Jha, X. Dou, S. Mun, Yanzhen Wang, Jae Gon Lee, D. Choi, O. Hu, S. Samavedam
{"title":"Transistor Optimization with Novel Cavity for Advanced FinFET Technology","authors":"H. Lo, Jianwei Peng, P. Zhao, E. Bazizi, Yue Hu, Y. Shi, Y. Qi, A. Vinslava, Y. Shen, W. Hong, H. Zang, Xing Zhang, A. Jha, X. Dou, S. Mun, Yanzhen Wang, Jae Gon Lee, D. Choi, O. Hu, S. Samavedam","doi":"10.1109/SISPAD.2018.8551703","DOIUrl":null,"url":null,"abstract":"We present a novel cavity engineering work – we named this cavity as dual-curvature cavity, which improves pFET electrical performance. This new cavity shape design minimizes the source/drain leakage penalty from deeper cavity depth while enabling the transistor performance benefits from larger eSiGe. In addition, this new cavity shape minimizes the penalty of deeper cavity on SDB (single diffusion break) devices through minimizing the facet effect in SDB structure. This work demonstrates that this new cavity shape could improve p-type transistor performance by 4{\\%} on top of the Fin shape optimization.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2018.8551703","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We present a novel cavity engineering work – we named this cavity as dual-curvature cavity, which improves pFET electrical performance. This new cavity shape design minimizes the source/drain leakage penalty from deeper cavity depth while enabling the transistor performance benefits from larger eSiGe. In addition, this new cavity shape minimizes the penalty of deeper cavity on SDB (single diffusion break) devices through minimizing the facet effect in SDB structure. This work demonstrates that this new cavity shape could improve p-type transistor performance by 4{\%} on top of the Fin shape optimization.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
