H. Bae, Jeong-Hyun Cho, Gyeong-Gu Kang, Yousung Park, Hyunsik Kim
{"title":"A 97.6%-Efficient 1-2MHz Hysteretic Buck Converter with 7V/μs DVS-Rate Enabled by Isosceles-Triangular Shunt Current Push-Pull Technique","authors":"H. Bae, Jeong-Hyun Cho, Gyeong-Gu Kang, Yousung Park, Hyunsik Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830181","DOIUrl":null,"url":null,"abstract":"This paper presents a fast dynamic voltage scaling (DVS) buck converter without losing high efficiency. The proposed isosceles-triangular shunt current (ITSC) push-pull technique allows a turning-point for optimal DVS to be independent of passive components while supplying sufficient current of 35A/μs. Current-tailing handover (CTH) realizes no voltage droop after DVS even under resistive loads. ITSC and CTH can also enhance load-transient response. The chip fabricated in 180-nm CMOS achieves 7V/μs DVS-rate and 97.6% peak efficiency.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830181","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a fast dynamic voltage scaling (DVS) buck converter without losing high efficiency. The proposed isosceles-triangular shunt current (ITSC) push-pull technique allows a turning-point for optimal DVS to be independent of passive components while supplying sufficient current of 35A/μs. Current-tailing handover (CTH) realizes no voltage droop after DVS even under resistive loads. ITSC and CTH can also enhance load-transient response. The chip fabricated in 180-nm CMOS achieves 7V/μs DVS-rate and 97.6% peak efficiency.