{"title":"Delay modeling for GaAs DCFL circuits","authors":"A. I. Kayssi, K. Sakallah","doi":"10.1109/GAAS.1993.394498","DOIUrl":null,"url":null,"abstract":"A timing macromodel for GaAs DCFL logic gates is derived. It circulates the delay of a gate as a function of such parameters as transistor sizes, capacitive loading, fanout, and input transition time. For NOR gates, the simultaneous switching of two inputs is also considered. Calculations based on the derived macromodel show excellent agreement with circuit simulation.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th Annual GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1993.394498","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A timing macromodel for GaAs DCFL logic gates is derived. It circulates the delay of a gate as a function of such parameters as transistor sizes, capacitive loading, fanout, and input transition time. For NOR gates, the simultaneous switching of two inputs is also considered. Calculations based on the derived macromodel show excellent agreement with circuit simulation.<>
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