A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate

T. Chiang, Chen Chih Yo, Hong-Wun Gao, Yeong-Her Wang
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Abstract

Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.
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建立了工作于亚阈值逻辑门的无结双栅极场效应管(JLDGFET)的噪声裕度和平均静态功率模型
基于器件和等效晶体管模型,我们提出了一种新的器件物理导向的静态噪声裕度(NM)、逻辑摆幅和平均功耗模型(Pave),用于工作在亚阈值CMOS逻辑门上的无结双栅极MOSFET (JLDGFET)。首先对JLDG MOSFET在低压条件下工作的NM和Pave进行了理论分析。厚硅厚度tsi、厚栅极氧化层厚度tox、大电源电压Vdd、短沟道长度Lg等器件参数由于严重的短沟道效应(SCEs),会导致纳米结构严重退化并产生较大的Pave。相反,小的亚阈值斜率和器件参数引起的平衡晶体管强度S都可以有效地抑制纳米退化并降低Pave。NM和Pave与DIBL类似,根据标度理论,它们都可以被标度因子唯一地控制和决定。
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