Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing

Abstract

This paper evaluates the radiation sensitivity of the Mirror and Hybrid Full Adders topologies at nominal and near-threshold voltage. The circuits are designed and electrical simulated adopting the 7 nm ASAP FinFET technology. Also, two mitigation approaches are considered on these circuits: Decoupling Cell and Transistor Sizing individually and combined. Considering soft errors, exploring Transistor Sizing increases $\boldsymbol{3}\mathrm{x}$ to $\boldsymbol{4}\mathrm{x}$ the robustness of the Mirror FA, for nominal and near-threshold operation, respectively. Both techniques reduces the total error occurrence over 35% for the investigated FAs circuits.