A 0.9GHz–5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio

A. Ng, S. Zheng, H. Leung, Y. Chao, H. Luong
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引用次数: 4

Abstract

A 0.9GHz-to-5.8GHz SDR RFE is presented employing a dual-band LNA with a switchable 3-coil transformer as loading for current-gain boosting and an automatic LO phase-error detection and calibration circuitry for harmonic rejection. Fabricated in 65nm CMOS and integrated with a fully-integrated all-digital synthesizer (ADFS), the RFE measures NF between 2.9dB and 3.8dB, IIP3 between -1.6dBm and -12.8dBm, 3rd-order HRR of 81dB, and 5th-order HRR of 70dB, while consuming between 66mA and 82mA from a 1.2V and occupying a total chip area of 4.2 mm2.
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0.9GHz-5.8GHz SDR接收机前端,具有基于变压器的电流增益增强和81 db的三阶谐波抑制比
提出了一种0.9 ghz至5.8 ghz SDR RFE,采用带可切换3圈变压器的双频LNA作为负载进行电流增益提升,并采用自动LO相位误差检测和校准电路进行谐波抑制。RFE采用65nm CMOS工艺,集成了全集成全数字合成器(ADFS),其NF测量范围为2.9 ~ 3.8dB, IIP3测量范围为-1.6 ~ -12.8dBm,三阶HRR为81dB,五阶HRR为70dB,功耗为66mA ~ 82mA,来自1.2V的总芯片面积为4.2 mm2。
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