A 4 to 5GHz Digitally Controlled Ring Oscillator with 100kHz Resolution using Noise Cancellation Technology in 40nm CMOS

Abstract

Herein a digitally controlled ring oscillator (DCRO) using noise cancellation technology is presented for an all digital phase-locked loops (ADPLLs) system. The design introduced a noise insensitive current source combined with current digital-to-analog converter (DAC) to achieve high resolution with wide tuning range, and better supply noise immunization. Meanwhile, regulated cascode topology is utilized to ensure the equality of drain source voltage of current mirror arrays under various current injecting into DCRO alleviating the channel-length modulation effect. The proposed design was implemented in 40 nm CMOS process operating from 4 to 5GHz with 100kHz resolution. Simulation results show that the supply sensitivity of current source can averagely reach -151.5dB and DCRO achieves static and dynamic supply noise immunity of 0.021 %-fout/1% VDD and 0.011 %-fout/1 %-VDD respectively at 4.5GHz. The overall power dissipation is 0.84mW from a 1.2V supply.