On the NBTI of Junction-less Nanowire and Novel Operation Scheme to Minimize NBTI Degradation in Analog Circuits

Abstract

Nano-wire (NW) transistor is expected to be used in sub-5nm technology nodes for its better electrostatic control. Junction-less (JL) NW is a feasible candidate, as steep source/drain junctions are not required. In this paper, Negative Bias-Temperature-Instability (NBTI) of JL-NW is studied through calibrated TCAD simulation. It is found that JL NW has 20 times less NBTI degradation (in terms of oxide/channel fixed charge generation) than regular NW because of40 times less hole carrier concentration at the oxide/channel interface and absence of field enhanced degradation. A novel operation scheme is then proposed to reduce NBTI degradation in analog circuit by switching the source and drain terminals periodically. The concept is verified through TCAD simulation of NW current mirror and it is found that NW NBTI degradation can befurther reduced by 25% to 35% by using the novel scheme.