Hardware Aspects of Iterative Receivers for V2X Applications

Abstract

In this paper we propose an iterative receiver architecture. The proposed architecture estimates the channel using a weighted function which combines both the coefficients estimated by the known pilot sequence and the decoded bit stream. This approach grants a performance boost of 1.5–2 dB in low bit error rates with the trade-off of more hardware resources utilized. A second, more complex architecture has been evaluated, but discarded as it does not produce any noticeable benefit.