Top-gated field effect devices using oxidized silicon nanowires

Abstract

The Si nanowires (SiNWs) used in these studies were synthesized by vapor-liquid-solid (VLS) growth from Au catalyst particles using 10% SiH 4 in H2 as the silicon gas source, trimethylboron (TMB) as the p-type dopant, and phosphine (PH3) as the n-type dopant. The ratio of TMB or PH3 to SiH4 was varied from 0 to 10-2 to modulate the hole or electron carrier concentration in the SiNWs. Following growth, the Au catalyst particles were removed from the tips of the as-grown SiNWs, and the wires were cleaned using a modified RCA process prior to dry thermal oxidation at 700degC for 4 hours. Transmission electron microscopy studies show that the interface between the SiNW core and the -10 nm thick SiO2 shell is smooth and uniform. These SiNWs were integrated onto a top- and back-gated test structure by electrofludically aligning individual wires between pairs of large area electrodes. Source and drain (S/D) contacts were defined by first removing the oxide shell at the NW tips and then lifting off Ti(100nm)/Au(60nm) metal. Non-self-aligned 3 mum long top gates comprised of Ti(60nm)/Au(40nm) were then deposited on the SiO2 shell, which served as the top gate dielectric. The n++ Si substrate coated with 100 nm of LPCVD Si3N4 was used as a back gate in these structures