Gate Stack Engineering in n-type (−201) $\upbeta-\text{Ga}_{2}\mathrm{O}_{3}$ Transistors

Abstract

A systematic study of Al2O3 and SiO2/ Al2O3 dielectric on p-Ga2O3 is carried out including the effect of the forming gas annealing. Capacitance-voltage (C-V) curve of the Al2O3/Ga2O3 gate stack shows a large hysteresis and sweep-to-sweep C-V shift compared to SiO2/Al2O3/Ga2O3 case, which suggests SiO2 interlayer reduces the defect density in Al2O3/Ga2O3 gate stack. In addition, forming gas annealing further suppresses the interface and border traps density in both Al2O3/Ga2O3 and SiO2/ Al2O3/Ga2O3 gate stacks. A thin film transistor (TFT) with annealed SiO2/ Al2O3 dielectric has an on-off ratio of ~106, a subthreshold swing (SS) of ~ 0.75 V/decade, and a hysteresis width $(\mathrm{V}_{\text{Hy}})$ of~ 0.5 V compared to an on-off ratio of~105, a SS of ~1.2 V/decade, and a VHy of ~2 V in the controlled TFT with unannealed Al2O3 dielectric. The increased on-off ratio by one order, reduced SS by > 400 mV/decade, and $\mathrm{V}_{\text{Hy}}$ by >1.5 V is attributed to decreased interface and border traps in annealed SiO2/ Al2O3 compared to unannealed Al2O3/Ga2O3 gate stack. Interface trap density is calculated by $\mathbf{V}_{\text{Hy}}$ of the transistor, which showed a five-time reduction in annealed SiO2/ Al2O3/Ga2O3 compared to the unannealed A;2O3/Ga2O3 gate stack. This study suggests that annealed SiO2/ Al2O3 dielectric stack is promising for $\boldsymbol{\upbeta}-\text{Ga}_2 \mathrm{O}_3$ transistors.