{"title":"Counter-lightly-doped-drain (C-LDD) structure for Multi-level cell (MLC) NOR flash memory free of drain disturb","authors":"Yimao Cai, Xing Zhang, Ru Huang","doi":"10.1109/ESSDERC.2011.6044198","DOIUrl":null,"url":null,"abstract":"This paper proposes a new structure with counter lightly doped drain (C-LDD) implantation for Multi-level cell (MLC) NOR flash memory application, aimed at reducing drain disturb. The manufacturing of C-LDD cell is fully compatible with standard floating gate flash process and no extra mask is required. Experimental results show that, by introducing C-LDD structure, the drain disturb can be successfully inhibited compared with conventional flash cell due to the optimization of drain junction doping profile. Endurance reliability is also improved when C-LDD is adopted. In addition, experiments reveal that no program degradation is observed when applying C-LDD implantation. These advantages have shown that C-LDD structure is a low cost and effective way to obtain high reliability in NOR flash memory.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2011.6044198","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper proposes a new structure with counter lightly doped drain (C-LDD) implantation for Multi-level cell (MLC) NOR flash memory application, aimed at reducing drain disturb. The manufacturing of C-LDD cell is fully compatible with standard floating gate flash process and no extra mask is required. Experimental results show that, by introducing C-LDD structure, the drain disturb can be successfully inhibited compared with conventional flash cell due to the optimization of drain junction doping profile. Endurance reliability is also improved when C-LDD is adopted. In addition, experiments reveal that no program degradation is observed when applying C-LDD implantation. These advantages have shown that C-LDD structure is a low cost and effective way to obtain high reliability in NOR flash memory.