A 0.25 /spl mu/m CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range

H. Sutoh, K. Yamakoshi, M. Ino
{"title":"A 0.25 /spl mu/m CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range","authors":"H. Sutoh, K. Yamakoshi, M. Ino","doi":"10.1109/CICC.1997.606581","DOIUrl":null,"url":null,"abstract":"This paper describes a wide frequency range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 /spl mu/m CMOS/SIMOX technology. This generator supports internal clock frequency to external clock frequency ratios of 2,4,8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 400 MHz. At 400 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606581","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

This paper describes a wide frequency range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 /spl mu/m CMOS/SIMOX technology. This generator supports internal clock frequency to external clock frequency ratios of 2,4,8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 400 MHz. At 400 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW.
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一个0.25 /spl mu/m CMOS/SIMOX锁相环时钟发生器嵌入门阵列LSI,锁定范围为5至400 MHz
本文介绍了一种采用0.25 /spl μ m CMOS/SIMOX技术嵌入门阵列LSI的宽频率范围锁相环时钟发生器。该发生器支持内部时钟频率与外部时钟频率比为2,4,8和16。锁相环有两种压控振荡器,可根据频率自动选择,从而扩大工作频率范围,同时保持低抖动。测量结果表明,锁相环工作在5 ~ 400mhz的锁相范围内。400mhz时,峰值抖动为50ps,电源电压为2v,功耗小于14mw。
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