A MOS-JFET Macromodel of SOI Four-Gate Transistors (G4FET) to Aid Innovative Circuit Design

Abstract

A MOS-JFET macromodel of silicon-on-insulator (SOI) four-gate transistor (G4FET) is presented in this paper to facilitate innovative circuit design with this novel multi-gate transistor. Designing interesting and innovative circuits with any new device requires a SPICE model that will work sufficiently well throughout the desired operating regions. A macromodel approach is adopted in this work which can provide a reasonably fast and accurate circuit simulation. Since G4FET combines the functionality of MOSFET and JFET devcies and robust, fast and reliable models of both MOSFET and JFET are already available, a macromodel combining these existing models is desirable from the perspective of a circuit designer. The model captures the essential interaction between multiple gates and accounts for both the volume and the surface conduction. In order to justify the feasibility of the macromodel, it is used to simulate two analog multiplier circuits which have been previously demonstrated experimentally and the simulation results match quite well with experimental findings.