A scalable ODC-based algorithm for RTL insertion of gated clocks

Abstract

This paper describes a new automatic clock-gating extraction working at the RT-level. The key features of our approach are: (i) seamless merging with existing industrial design flows and commercial tools; (ii) high scalability to deal with large circuits; (iii) improved quality of results with respect to available commercial tools; (iv) smaller and well-controlled overhead in speed and area. Experimental results, on a set of industrial RTL designs, demonstrate the viability and practical impact of our approach.