A functional verification environment for advanced switching architecture

Abstract

In this paper, intra-chip design has long been the main research area for the past years, resulting in several folds of computing power increase per year. In contrast, the speed of cross-chip connection, or even cross-system connection, has not been enhanced at the same rate, and gradually became the bottleneck of current computing systems. PCI, PCI-X, and PCI-Express epitomize the evolvement of our peripheral connecting strategy. By radical change in architecture, we successfully increase throughput of connection facilities in one autonomous system. We propose a architecture for verifying advanced switch hardware. Also successfully verify the compliance of the design under test's features to the given protocol.