Amplifier design approximations in submicron CMOS

Abstract

This paper demonstrates the design of analog circuits using simulated I/V data of a sample device (PMOS/NMOS), and estimation of transconductance (gm) from this plot using approximation. Proposed design technique is based on the fact that the ratio of transconductance (gm) is inversely proportional to the MOS gate-source voltage (VGS). From the amplifier specifications, bias current and the load (or DC drop across the load) are generally estimated which in-turn is used to predict the device size. Proposed method is not only technology independent, it is also free from complex mathematical expressions associated with the device as it employs plots generated from simulators, Instead of analytical methods usually based on square law, which is unfit to capture sub-micron characteristics. When simulator is incorporated in the design process, analysis of the designed circuit, using the same simulator, is expected to match the desired performance closely. Using this simple approach, design time becomes shorter and a workable design can be made very quickly. An example amplifier circuit is designed using the proposed method, and simulation results are presented.