S. Maeda, Masanori Tanaka, Yoko Otsuka, Akinobu Watanabe, Masayuki Tsukuda, Y. Morishita
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引用次数: 3
Abstract
We propose new ESD design concept using power clamps distributed outside I/O cell ring, which enables the reduction of chip area by the removal of dead space in the chip core area with no degradation of ESD robustness. Our effective design was demonstrated with 40nm MCU test-chip.
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