X-Aware verification: A different perspective!

Abstract

Verification techniques such as Clock Domain Crossing (CDC) and Power-Aware verification are early ways to detect and debug silicon related bugs. One crucial problem is having an X-state that leads to mismatching behavior between synthesis and RTL. This paper describes how the X-problem affects CDC synchronization correctness and the power intent of the design and shows how the current protocol checking techniques misses real faults that occur due to having an X. Also, it proposes two methods to account for X in the current CDC and power aware verification. The paper provides a case study to prove the feasibility and usefulness of the approach proposed.