Pub Date : 2017-01-03DOI: 10.1109/ICECS.2013.6815345
F. Taher, H. Al-Ahmad, N. Werghi
Lung cancer has been the largest cause of cancer deaths worldwide with an overall 5-year survival rate of only 15%. Its symptoms can be detected only in advanced stages where the patient's chance of survival is very low, thus causing the mortality rate to be the highest among all other types of cancer.
{"title":"Early detection of lung cancer based on sputum color image analysis","authors":"F. Taher, H. Al-Ahmad, N. Werghi","doi":"10.1109/ICECS.2013.6815345","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815345","url":null,"abstract":"Lung cancer has been the largest cause of cancer deaths worldwide with an overall 5-year survival rate of only 15%. Its symptoms can be detected only in advanced stages where the patient's chance of survival is very low, thus causing the mortality rate to be the highest among all other types of cancer.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129809203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-02-17DOI: 10.1109/ICECS.2013.6815469
Deborah L. Gater, Attya Iqbal, Jeffrey Davey, E. Gale
Memristors have been suggested as neuromorphic computing elements. Spike-time dependent plasticity and the Hodgkin-Huxley model of the neuron have both been modelled effectively by memristor theory. The d.c. response of the memris-tor is a current spike. Based on these three facts we suggest that memristors are well-placed to interface directly with neurons. In this paper we show that connecting a spiking memristor network to spiking neuronal cells causes a change in the memristor network dynamics by: causing a change in current decay rate consistent with a change in memristor state; presenting more-linear I-t dynamics; and increasing the memristor spiking rate, as a consequence of interaction with the spiking neurons. This demonstrates that neurons are capable of communicating directly with memristors, without the need for computer translation.
{"title":"Connecting spiking neurons to a spiking memristor network changes the memristor dynamics","authors":"Deborah L. Gater, Attya Iqbal, Jeffrey Davey, E. Gale","doi":"10.1109/ICECS.2013.6815469","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815469","url":null,"abstract":"Memristors have been suggested as neuromorphic computing elements. Spike-time dependent plasticity and the Hodgkin-Huxley model of the neuron have both been modelled effectively by memristor theory. The d.c. response of the memris-tor is a current spike. Based on these three facts we suggest that memristors are well-placed to interface directly with neurons. In this paper we show that connecting a spiking memristor network to spiking neuronal cells causes a change in the memristor network dynamics by: causing a change in current decay rate consistent with a change in memristor state; presenting more-linear I-t dynamics; and increasing the memristor spiking rate, as a consequence of interaction with the spiking neurons. This demonstrates that neurons are capable of communicating directly with memristors, without the need for computer translation.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-09DOI: 10.1109/ICECS.2013.6815457
Rui Yang, Jianguo Wang, B. Clement, A. Mansour
Field-Programmable Gate Array (FPGA) offers advantages for many applications, particularly where missions are complex and time performance is critical. For small-production digital acoustic synthesizers, FPGA can achieve the above-mentioned tighter system requirements with low total system costs on single chip. In this manuscript, a real-time acoustic synthesizer is implemented using Fourier series algorithm on Altera's Cyclone II FPGA chip. This work emphasizes systematic designs and parallel computations. The proposed system includes a flexible processor and a parallel parameterized acoustic module. On one hand, the Nios II embedded processor, which is relatively low-speed component, is used to generate commands and configure high-speed acoustic module parameters. On the other hand, acoustic module which should require high-speed components contains 4 parallel architectures to gain high-speed simultaneous calculus of 4 independent digital timbres. Every timbre is equivalent to 16 parallel high-precision harmonic channels with 0.3 % frequency error. Experimental results corroborate the fact that a single FPGA chip can achieve complex missions and attain real-time performances.
现场可编程门阵列(FPGA)为许多应用提供了优势，特别是在任务复杂和时间性能至关重要的情况下。对于小批量生产的数字声学合成器，FPGA可以在单片上以较低的系统总成本实现上述更严格的系统要求。在这篇论文中，使用傅立叶级数算法在Altera的Cyclone II FPGA芯片上实现了实时声学合成器。这项工作强调系统设计和并行计算。该系统包括一个柔性处理器和一个并行参数化声学模块。一方面，使用Nios II嵌入式处理器这一相对低速的部件，生成命令并配置高速声学模块参数。另一方面，声学模块需要高速组件，包含4个并行架构，以获得4个独立数字音色的高速同时演算。每个音色相当于16个平行的高精度谐波通道，频率误差为0.3%。实验结果证实了单个FPGA芯片可以实现复杂的任务和实时性。
{"title":"FPGA implementation of a parameterized Fourier synthesizer","authors":"Rui Yang, Jianguo Wang, B. Clement, A. Mansour","doi":"10.1109/ICECS.2013.6815457","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815457","url":null,"abstract":"Field-Programmable Gate Array (FPGA) offers advantages for many applications, particularly where missions are complex and time performance is critical. For small-production digital acoustic synthesizers, FPGA can achieve the above-mentioned tighter system requirements with low total system costs on single chip. In this manuscript, a real-time acoustic synthesizer is implemented using Fourier series algorithm on Altera's Cyclone II FPGA chip. This work emphasizes systematic designs and parallel computations. The proposed system includes a flexible processor and a parallel parameterized acoustic module. On one hand, the Nios II embedded processor, which is relatively low-speed component, is used to generate commands and configure high-speed acoustic module parameters. On the other hand, acoustic module which should require high-speed components contains 4 parallel architectures to gain high-speed simultaneous calculus of 4 independent digital timbres. Every timbre is equivalent to 16 parallel high-precision harmonic channels with 0.3 % frequency error. Experimental results corroborate the fact that a single FPGA chip can achieve complex missions and attain real-time performances.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128533262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-08DOI: 10.1109/ICECS.2013.6815549
Felipe Rosa, Luciano Ost, R. Reis, G. Sassatelli
The software complexity of MPSoCs is increasing dramatically, resulting in new design challenges, such as improving the system's performance and programmability by porting parallel programming APIs. Such challenges impose more time and cost on the system's software development. This leads to the adopting of virtual platform frameworks aimed at functional verification like OVP, capable of simulating embedded systems running real application code at the speed of hundreds of MIPS. This work focuses on enhancing OVP capability by including a quasi-cycle accurate timing CPU model, making it suitable for performance analysis. This paper also evaluates the accuracy of the proposed timing CPU model when compared to a real system. Results show that the accuracy of our model varies from 0.06% to 10.56% depending on the benchmark profile.
{"title":"Instruction-driven timing CPU model for efficient embedded software development using OVP","authors":"Felipe Rosa, Luciano Ost, R. Reis, G. Sassatelli","doi":"10.1109/ICECS.2013.6815549","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815549","url":null,"abstract":"The software complexity of MPSoCs is increasing dramatically, resulting in new design challenges, such as improving the system's performance and programmability by porting parallel programming APIs. Such challenges impose more time and cost on the system's software development. This leads to the adopting of virtual platform frameworks aimed at functional verification like OVP, capable of simulating embedded systems running real application code at the speed of hundreds of MIPS. This work focuses on enhancing OVP capability by including a quasi-cycle accurate timing CPU model, making it suitable for performance analysis. This paper also evaluates the accuracy of the proposed timing CPU model when compared to a real system. Results show that the accuracy of our model varies from 0.06% to 10.56% depending on the benchmark profile.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125871419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-08DOI: 10.1109/ICECS.2013.6815450
J. Nebhen, E. Savary, W. Rahajandraibe, C. Dufaza, S. Meillére, F. Haddad, E. Kussener, H. Barthélemy, J. Czarny, A. Walther
The design and implementation of a CMOS integrated analog to digital interface dedicated to hybrid integration of MEMS resistive microphone is presented. Audio sensing is achieved with an innovative low-cost technology that uses single crystal piezoresistive silicon nanowires as transducer in a MEMS. The circuit composed of a low-noise instrumentation preamplifier followed by a single bit fourth order continuous-time sigma-delta modulator (CT-ΣΔM) includes bias circuit for sensor. To join low power applications where extensive digital processing is employed, 0.28 μm CMOS process with a 2.5 V supply has been adopted. The test chip occupies an area of 1 mm2. Post-layout simulation exhibits promising performances where noise density is below 8 nV/VHz within the frequency range from 10 Hz to 10 kHz. Complete interface circuit features a current consumption of 2.4 mA.
{"title":"Low-noise CMOS analog-to-digital interface for MEMS resistive microphone","authors":"J. Nebhen, E. Savary, W. Rahajandraibe, C. Dufaza, S. Meillére, F. Haddad, E. Kussener, H. Barthélemy, J. Czarny, A. Walther","doi":"10.1109/ICECS.2013.6815450","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815450","url":null,"abstract":"The design and implementation of a CMOS integrated analog to digital interface dedicated to hybrid integration of MEMS resistive microphone is presented. Audio sensing is achieved with an innovative low-cost technology that uses single crystal piezoresistive silicon nanowires as transducer in a MEMS. The circuit composed of a low-noise instrumentation preamplifier followed by a single bit fourth order continuous-time sigma-delta modulator (CT-ΣΔM) includes bias circuit for sensor. To join low power applications where extensive digital processing is employed, 0.28 μm CMOS process with a 2.5 V supply has been adopted. The test chip occupies an area of 1 mm2. Post-layout simulation exhibits promising performances where noise density is below 8 nV/VHz within the frequency range from 10 Hz to 10 kHz. Complete interface circuit features a current consumption of 2.4 mA.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121915321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-08DOI: 10.1109/ICECS.2013.6815334
D. Mellouli, H. Mnif, D. Cordeau, M. Loulou, J. Paillot
During the past decade, coupled oscillators have shown their efficiency as simple methods for phase control in microwave antenna arrays, and hence as alternatives to conventional electronic beam steering methods. This paper describes the design and the implementation of a fully monolithic coupled-oscillator array, operating at 6 GHz in 0.25 μm BICMOS SiGe process. A novel and original method, based on the use of a MOS transistor, for coupling the differential oscillators is developed and presented. At 2.5 V power supply voltage, and a power dissipation of only 62.5 mW, the coupled oscillators array features a simulated phase noise of -124.8 dBc/Hz at 1 MHz frequency offset from a 6.01 GHz carrier, giving a simulated phase progression that was continuously variable over the range -84 ° <; Δ□ <; 84 ° and -96° <; Δ□ <; 96°.
{"title":"Design and implementation of a 6-GHz array of two differential oscillators coupled through a MOS transistor network","authors":"D. Mellouli, H. Mnif, D. Cordeau, M. Loulou, J. Paillot","doi":"10.1109/ICECS.2013.6815334","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815334","url":null,"abstract":"During the past decade, coupled oscillators have shown their efficiency as simple methods for phase control in microwave antenna arrays, and hence as alternatives to conventional electronic beam steering methods. This paper describes the design and the implementation of a fully monolithic coupled-oscillator array, operating at 6 GHz in 0.25 μm BICMOS SiGe process. A novel and original method, based on the use of a MOS transistor, for coupling the differential oscillators is developed and presented. At 2.5 V power supply voltage, and a power dissipation of only 62.5 mW, the coupled oscillators array features a simulated phase noise of -124.8 dBc/Hz at 1 MHz frequency offset from a 6.01 GHz carrier, giving a simulated phase progression that was continuously variable over the range -84 ° <; Δ□ <; 84 ° and -96° <; Δ□ <; 96°.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130157047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-08DOI: 10.1109/ICECS.2013.6815431
Hassan Anwar, M. Daneshtalab, M. Ebrahimi, J. Plosila, H. Tenhunen
Increased demand for data security is an undeniable fact. Towards achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. In this paper, we present a crypto processor using Advanced Encryption Standard (AES). The AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully pipelined module which follows inner round and outer round pipeline design. The results show that the presented pipeline version of the AES algorithm along with MIPS processor outperforms traditional methods. At the operating frequency of 553 MHz, the proposed design can achieve the throughput of 58 Gbps, the latency of 240 ns, and the minimum power consumption of 76 mw.
{"title":"FPGA implementation of AES-based crypto processor","authors":"Hassan Anwar, M. Daneshtalab, M. Ebrahimi, J. Plosila, H. Tenhunen","doi":"10.1109/ICECS.2013.6815431","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815431","url":null,"abstract":"Increased demand for data security is an undeniable fact. Towards achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. In this paper, we present a crypto processor using Advanced Encryption Standard (AES). The AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully pipelined module which follows inner round and outer round pipeline design. The results show that the presented pipeline version of the AES algorithm along with MIPS processor outperforms traditional methods. At the operating frequency of 553 MHz, the proposed design can achieve the throughput of 58 Gbps, the latency of 240 ns, and the minimum power consumption of 76 mw.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133597762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-08DOI: 10.1109/ICECS.2013.6815460
Marcelo G. Mandelli, Felipe Rosa, Luciano Ost, G. Sassatelli, F. Moraes
Multiprocessor SoCs (MPSoCs) have rapidly evolved towards high-performance heterogeneous computing systems designed under performance, power efficiency and scalability concerns. Such systems accomplish billions of operations per second moving towards hundreds of processing elements that communicate through a network-on-chip. The hardware and software complexity of such systems is increasing dramatically, resulting in new design challenges, such as providing scalable modeling facilities and verification for both hardware and software. This work proposes a multi-level design approach for MPSoCs, targeting the reduction of software development cycle. The paper also presents different scenarios for exploration purposes, showing the benefits in term of design space exploration for to the proposed environment.
{"title":"Multi-level MPSoC modeling for reducing software development cycle","authors":"Marcelo G. Mandelli, Felipe Rosa, Luciano Ost, G. Sassatelli, F. Moraes","doi":"10.1109/ICECS.2013.6815460","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815460","url":null,"abstract":"Multiprocessor SoCs (MPSoCs) have rapidly evolved towards high-performance heterogeneous computing systems designed under performance, power efficiency and scalability concerns. Such systems accomplish billions of operations per second moving towards hundreds of processing elements that communicate through a network-on-chip. The hardware and software complexity of such systems is increasing dramatically, resulting in new design challenges, such as providing scalable modeling facilities and verification for both hardware and software. This work proposes a multi-level design approach for MPSoCs, targeting the reduction of software development cycle. The paper also presents different scenarios for exploration purposes, showing the benefits in term of design space exploration for to the proposed environment.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116098522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-08DOI: 10.1109/ICECS.2013.6815510
F. Haddad, W. Rahajandraibe, H. Aziza, K. Castellani-Coulié, J. Portal, J. Nebhen, H. Barthélemy
A low-cost auto-calibration technique of Radio-Frequency (RF) Passive Polyphase Filter (PPF) for high image rejection in low Intermediate Frequency receiver is presented. The resistance values of the filter are process and temperature dependent with great mismatch constraints especially in the RF domain. That can severely impact the circuit performances if not controlled. In order to overcome this limitation, an in-line auto-calibration of the PPF resistance values, based on Design Of Experiment (DOE) methodology, is presented. Using DOE, a model is derived from thermal and process deviations of the chip responses. This approach results in a robust and low-cost solution.
{"title":"Low-cost auto-calibration of passive polyphase filter in image reject receiver","authors":"F. Haddad, W. Rahajandraibe, H. Aziza, K. Castellani-Coulié, J. Portal, J. Nebhen, H. Barthélemy","doi":"10.1109/ICECS.2013.6815510","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815510","url":null,"abstract":"A low-cost auto-calibration technique of Radio-Frequency (RF) Passive Polyphase Filter (PPF) for high image rejection in low Intermediate Frequency receiver is presented. The resistance values of the filter are process and temperature dependent with great mismatch constraints especially in the RF domain. That can severely impact the circuit performances if not controlled. In order to overcome this limitation, an in-line auto-calibration of the PPF resistance values, based on Design Of Experiment (DOE) methodology, is presented. Using DOE, a model is derived from thermal and process deviations of the chip responses. This approach results in a robust and low-cost solution.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124813265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815542
H. Tawfik, M. El-Gamal, F. Nabki
This paper presents a mechanism that involves the integration of a pixel blind to infrared (IR) radiation into a focal plane array (FPA) for thermal detection. The blind pixel serves as a reference capacitor while scanning the FPA active pixels. In harsh environment conditions (e.g. shocks and wide changes in ambient temperature), this mechanism yields down to a 0.83% percent error in the measured signal which is demonstrated here by simulations. The active and blind pixels design, fabrication process, and materials selection are discussed with the aid of finite element analysis.
{"title":"Shock rejection & ambient temperature compensation mechanism for uncooled micocantilever thermal detector","authors":"H. Tawfik, M. El-Gamal, F. Nabki","doi":"10.1109/ICECS.2013.6815542","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815542","url":null,"abstract":"This paper presents a mechanism that involves the integration of a pixel blind to infrared (IR) radiation into a focal plane array (FPA) for thermal detection. The blind pixel serves as a reference capacitor while scanning the FPA active pixels. In harsh environment conditions (e.g. shocks and wide changes in ambient temperature), this mechanism yields down to a 0.83% percent error in the measured signal which is demonstrated here by simulations. The active and blind pixels design, fabrication process, and materials selection are discussed with the aid of finite element analysis.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115233960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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