Delay and area optimization in standard-cell design

Abstract

A heuristic approach to the optimal selection of standard cells in VLSI circuit design is presented. A cell library is composed of several templates (3-5) for each type of cell. These templates differ in area, driving capabilities, intrinsic delay, and capacitive loading. When realizing a logically synthesized circuit, one selects the best templates from the cell library to minimize the total area of the cells under delay constraints. The algorithm is capable of handling efficiently relatively large designs taking into account the entire circuit, not iterating on a path basis. Carefully chosen weights reflect the significance of particular cells in the circuit and guide the template selection process. Because the algorithm is capable of increasing and decreasing the templates, very good experimental results are achieved.<>