Gate-All-Around Si-Nanowire Transistors: Simulation at Nanoscale

Abstract

With downscaling of device features to nanoscale, quantum effect plays an important role to understand the device physics. When the cross-section of the channel becomes closer to the free electron wavelength, quantum corrections are essential for accurate modeling of the electrostatic properties of the device. As technology scaling continues, the lateral nanowire transistor (LNW) size is expected to be scaled down from 7nm to 5nm or below. Local continuum models can no longer accurately describe nanoscale device behavior and hence more advanced physics-based models must be adopted in device simulation. Technology Computer Aided Design (TCAD) based on Density-Gradient and Drift-Diffusion models is a powerful tool to support the technology development in the semiconductor industry. The main focus of this study is to compare two device modelling approaches for the performance evaluation of double-stacked nanoscale gate-all-around Si nanowire transistors in which advanced transport models are included in simulation.