Design of Logical Control Units Based on Finite State Machines' Patterns

Abstract

In this work it is offered to use patterns of automata-based programming for designing logical control devices on the basis of finite state machines. To describe the functioning algorithm of the automatic logical control device, it is suggested to use the temporal state diagram, which takes into account real time delays for each states of finite states machine. During designing a state machine based on FPGA platform, the functioning algorithm is described in the VHDL hardware description language, and the device is synthesized in the CAD XILINX ISE, and, when the design of finite state machine based on the microcontroller (family MCS 51), the functioning algorithm is described on the subset of the C language using the Keil development tool.