{"title":"An ultra-small capacitor-less LDO with controlled-resistance technique and MOSFET-only bandgap","authors":"Long Nguyen, K. Le, Loan Pham-Nguyen Hanoi","doi":"10.1109/ATC.2015.7388354","DOIUrl":null,"url":null,"abstract":"In this paper, we propose an ultra-small low dropout regulator (LDO) for NFC tag combining two new techniques. Firstly, a voltage bandgap is designed using only MOSFET instead of BJT in conventional architecture to reduce significantly the chip size. Secondly, to increase the stability of LDO we proposed a controlled circuit to vary output resistance according to output-load current. The latter technique also allows removing the feedback capacitor normally used in a conventional LDO architecture. The proposed LDO has a stable output voltage at 1.8V with input voltage varying from 2.1V to 3.3 V, a maximum current of 10 mA, and only 0.0058 mm2 chip area.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Advanced Technologies for Communications (ATC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATC.2015.7388354","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, we propose an ultra-small low dropout regulator (LDO) for NFC tag combining two new techniques. Firstly, a voltage bandgap is designed using only MOSFET instead of BJT in conventional architecture to reduce significantly the chip size. Secondly, to increase the stability of LDO we proposed a controlled circuit to vary output resistance according to output-load current. The latter technique also allows removing the feedback capacitor normally used in a conventional LDO architecture. The proposed LDO has a stable output voltage at 1.8V with input voltage varying from 2.1V to 3.3 V, a maximum current of 10 mA, and only 0.0058 mm2 chip area.