Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388339
C. Phung, V. Nguyen, T. Nguyen
Network coding is a new communication paradigm which allows network nodes not only to forward packets but also to combine them together to reduce the number of transmissions. COPE has been the first network coding scheme designed for unicast traffic in wireless networks. COPE-based network coding-aware routing optimization has been proposed to improve network performances. However, it is interesting to study network coding-aware routing optimization using other network coding schemes to analyze the impact of coding conditions. In this paper, we study the problem of network coding-aware routing optimization using BEND, an extension of COPE. We model the coding structures of BEND and integrate them into the routing optimization problem. The simulation results show that BEND-aware routing can improve network throughput by creating more coding structures than COPE.
{"title":"BEND-aware routing optimization in wireless mesh networks","authors":"C. Phung, V. Nguyen, T. Nguyen","doi":"10.1109/ATC.2015.7388339","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388339","url":null,"abstract":"Network coding is a new communication paradigm which allows network nodes not only to forward packets but also to combine them together to reduce the number of transmissions. COPE has been the first network coding scheme designed for unicast traffic in wireless networks. COPE-based network coding-aware routing optimization has been proposed to improve network performances. However, it is interesting to study network coding-aware routing optimization using other network coding schemes to analyze the impact of coding conditions. In this paper, we study the problem of network coding-aware routing optimization using BEND, an extension of COPE. We model the coding structures of BEND and integrate them into the routing optimization problem. The simulation results show that BEND-aware routing can improve network throughput by creating more coding structures than COPE.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127267017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388411
P. Ngoc, Tran Trung Duy, Vo Nguyen Quoc Bao, Khuong Ho‐Van
In this paper, we investigate two partial relay selection (PRS) protocols in underlay cognitive radio under impact of hardware impairment. In particular, the re-active and pro-active PRS schemes are proposed to compensate the performance loss due to the hardware noises and the interference constraints required by multiple primary users (PUs). Moreover, incremental relaying technique is also used to enhance spectrum efficiency. For performance evaluation and comparison, we drive exact and asymptotic closed-form expressions of outage probability over Rayleigh fading channel. Finally, Monte Carlo simulations are presented to verify the analytical derivations.
{"title":"Performance enhancement for underlay cognitive radio with partial relay selection methods under impact of hardware impairment","authors":"P. Ngoc, Tran Trung Duy, Vo Nguyen Quoc Bao, Khuong Ho‐Van","doi":"10.1109/ATC.2015.7388411","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388411","url":null,"abstract":"In this paper, we investigate two partial relay selection (PRS) protocols in underlay cognitive radio under impact of hardware impairment. In particular, the re-active and pro-active PRS schemes are proposed to compensate the performance loss due to the hardware noises and the interference constraints required by multiple primary users (PUs). Moreover, incremental relaying technique is also used to enhance spectrum efficiency. For performance evaluation and comparison, we drive exact and asymptotic closed-form expressions of outage probability over Rayleigh fading channel. Finally, Monte Carlo simulations are presented to verify the analytical derivations.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125077281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388326
P. Bousseaud, E. Novakov, J. Fournier
A low power Software-Defined radio receiver operating between 400 MHz and 1.5 GHz is presented in this paper. The receiver is based on differential switched 4-path passive mixer architecture. The sampling frequency fixes the carrier frequency of the received signal and a simple RC time constant determines the receiver bandwidth. The mixer structure permits to implement flexible high-Q band-pass filters at the RF side. This receiver has improved linearity and is robust to strong out-of-band blockers and adjacent channel interferences. A wide-band 15 dB gain LNA permits to achieve a noise figure less than 4 dB between 400 MHz and 1.5 GHz. The measured sensitivity is -83 dBm with an overall gain of 55 dB over the chain. The IIP3 of the receiver is -22.7 dBm and the power consumption is 45.7 mW under a 1.2V power supply voltage. The IC receiver has been designed in a 130nm CMOS process. The receiver is suitable for Internet of Things (IoT) applications.
{"title":"A direct RF signal sampling integrated receiver for IoT applications","authors":"P. Bousseaud, E. Novakov, J. Fournier","doi":"10.1109/ATC.2015.7388326","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388326","url":null,"abstract":"A low power Software-Defined radio receiver operating between 400 MHz and 1.5 GHz is presented in this paper. The receiver is based on differential switched 4-path passive mixer architecture. The sampling frequency fixes the carrier frequency of the received signal and a simple RC time constant determines the receiver bandwidth. The mixer structure permits to implement flexible high-Q band-pass filters at the RF side. This receiver has improved linearity and is robust to strong out-of-band blockers and adjacent channel interferences. A wide-band 15 dB gain LNA permits to achieve a noise figure less than 4 dB between 400 MHz and 1.5 GHz. The measured sensitivity is -83 dBm with an overall gain of 55 dB over the chain. The IIP3 of the receiver is -22.7 dBm and the power consumption is 45.7 mW under a 1.2V power supply voltage. The IC receiver has been designed in a 130nm CMOS process. The receiver is suitable for Internet of Things (IoT) applications.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126123068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388311
L. X. Truong, Vũ Quang Tạo, T. M. Tuan, T. Giang
In this paper, a compact design for bandwidth enhancement of microstrip antenna is present. A basic rectangle microstrip is selected to research. The ground element of the proposed antenna is taken in the form of Defected Ground Structure (DGS). The antenna is based on substance Duroid RO4700JXR and is fed by a feeding microstrip line. The results of a fabricated antenna have an agreement with simulation results with wide bandwidth and good return loss.
{"title":"Design a microstrip antenna with defected ground structure","authors":"L. X. Truong, Vũ Quang Tạo, T. M. Tuan, T. Giang","doi":"10.1109/ATC.2015.7388311","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388311","url":null,"abstract":"In this paper, a compact design for bandwidth enhancement of microstrip antenna is present. A basic rectangle microstrip is selected to research. The ground element of the proposed antenna is taken in the form of Defected Ground Structure (DGS). The antenna is based on substance Duroid RO4700JXR and is fed by a feeding microstrip line. The results of a fabricated antenna have an agreement with simulation results with wide bandwidth and good return loss.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125315460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388336
Thai Van Nguyen, T. Do, D. Vo
This paper proposes a novel image quality enhancement method using fuzzy filter and texture map. The texture map of the original images or the compressed images is estimated and then is used to control the strength's filter. The task is to reduce blocking artifacts while preserving the sharpness of decompressed images. The simulation results show that the proposed fuzzy filtering scheme achieves the best visual quality and PSNR among the simulated methods.
{"title":"Advanced texture-adapted blocking removal for compressed visual content","authors":"Thai Van Nguyen, T. Do, D. Vo","doi":"10.1109/ATC.2015.7388336","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388336","url":null,"abstract":"This paper proposes a novel image quality enhancement method using fuzzy filter and texture map. The texture map of the original images or the compressed images is estimated and then is used to control the strength's filter. The task is to reduce blocking artifacts while preserving the sharpness of decompressed images. The simulation results show that the proposed fuzzy filtering scheme achieves the best visual quality and PSNR among the simulated methods.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115564566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388409
N. T. Nguyen, S. V. Tran, Duong Nguyen, Linh Mai
In this paper, an S-band mixer circuit used for both up- and down- conversion mixers is designed. The proposed mixer works in the range power levels from -20dBm to -3 dBm for the RF input of the down-converter, and for the IF input of the up-converter. The Local oscillator (LO) working at 2.87 GHz has the power level of +2dBm. The simulation and measurement exhibits the conversion loss greater than -10dB and good isolation between RF, IF, and LO ports (RF-LO isolation >30 dB, LO-IF isolation>30 dB, RF-IF isolation>25 dB).
{"title":"Design and implement a single balanced mixer at S band","authors":"N. T. Nguyen, S. V. Tran, Duong Nguyen, Linh Mai","doi":"10.1109/ATC.2015.7388409","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388409","url":null,"abstract":"In this paper, an S-band mixer circuit used for both up- and down- conversion mixers is designed. The proposed mixer works in the range power levels from -20dBm to -3 dBm for the RF input of the down-converter, and for the IF input of the up-converter. The Local oscillator (LO) working at 2.87 GHz has the power level of +2dBm. The simulation and measurement exhibits the conversion loss greater than -10dB and good isolation between RF, IF, and LO ports (RF-LO isolation >30 dB, LO-IF isolation>30 dB, RF-IF isolation>25 dB).","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128544315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To deal with inference and reasoning problems, Gaussian process has been considered as a promising tool due to the robustness and flexibility features. Especially, solving the regression and classification, Gaussian process coupling with Bayesian learning is one of the most appropriate supervised learning approaches in terms of accuracy and tractability. Unfortunately, this combination tolerates high complexity from computation and data storage. Obviously, this limitation makes Gaussian process ill-equipped to deal with the systems requiring fast response time. In this paper, the research focuses on analyzing the performance issue of Gaussian process, developing a method to reduce the complexity and implementing to predict CPU utilization, which is used as a factor to predict the status of computing node. Subsequently, a migration mechanism is applied so as to migrate the system-level processes between CPU cores and turn off the idle ones in order to save the energy while still maintaining the performance.
{"title":"Complexity reduction for Gaussian process regression in spatio-temporal prediction","authors":"Dinh-Mao Bui, Thien Huynh-The, Sungyoung Lee, Yongik Yoon","doi":"10.1109/ATC.2015.7388344","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388344","url":null,"abstract":"To deal with inference and reasoning problems, Gaussian process has been considered as a promising tool due to the robustness and flexibility features. Especially, solving the regression and classification, Gaussian process coupling with Bayesian learning is one of the most appropriate supervised learning approaches in terms of accuracy and tractability. Unfortunately, this combination tolerates high complexity from computation and data storage. Obviously, this limitation makes Gaussian process ill-equipped to deal with the systems requiring fast response time. In this paper, the research focuses on analyzing the performance issue of Gaussian process, developing a method to reduce the complexity and implementing to predict CPU utilization, which is used as a factor to predict the status of computing node. Subsequently, a migration mechanism is applied so as to migrate the system-level processes between CPU cores and turn off the idle ones in order to save the energy while still maintaining the performance.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"436 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128374674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388305
Hiếu Nguyễn Minh, Dang Nguyen Quoc, Trang Hoang
A design of a 10-bit 25 MS/s Successive Approximation Register (SAR) Analog to Digital Converter (ADC) that uses improved dynamic comparator has been introduced in this paper. In this improved dynamic comparator, a novel pre-amplifier is proposed in order to enhance the bandwidth up to 817 MHz when compared to classical pre-amplifier structures. Besides, a modified dynamic latch with driving simultaneously gate and bulk terminals are also presented in this work. The whole of SAR ADC is designed and simulated in 180nm CMOS process with the structure based on the conventional architecture but reduced the capacitor array mismatch by using separated clock frequencies to control simultaneously comparator and SAR combination logic. Thus, this design works with the clock frequency of 0.5 GHz achieving a maximum sampling rate at 25 MS/s and 1.8V supply voltage. Without calibration technique, sampling at 25 MS/s, peak DNL and peak INL of original ADCs averaged across the array are 0.7 least significant bit (LSB) and 3.6 LSB, respectively.
{"title":"A design of 10-bit 25-MS/s SAR ADC using separated clock frequencies with high speed comparator in 180nm CMOS","authors":"Hiếu Nguyễn Minh, Dang Nguyen Quoc, Trang Hoang","doi":"10.1109/ATC.2015.7388305","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388305","url":null,"abstract":"A design of a 10-bit 25 MS/s Successive Approximation Register (SAR) Analog to Digital Converter (ADC) that uses improved dynamic comparator has been introduced in this paper. In this improved dynamic comparator, a novel pre-amplifier is proposed in order to enhance the bandwidth up to 817 MHz when compared to classical pre-amplifier structures. Besides, a modified dynamic latch with driving simultaneously gate and bulk terminals are also presented in this work. The whole of SAR ADC is designed and simulated in 180nm CMOS process with the structure based on the conventional architecture but reduced the capacitor array mismatch by using separated clock frequencies to control simultaneously comparator and SAR combination logic. Thus, this design works with the clock frequency of 0.5 GHz achieving a maximum sampling rate at 25 MS/s and 1.8V supply voltage. Without calibration technique, sampling at 25 MS/s, peak DNL and peak INL of original ADCs averaged across the array are 0.7 least significant bit (LSB) and 3.6 LSB, respectively.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121298712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388388
Tanh Minh Ly, D. Vo
This paper proposes a novel algorithm to automatically solve a Sudoku puzzle on images taken from magazines or computer game software. The process involves preprocessing the image, extracting characters, recognizing characters and solving puzzle, which all are specifically designed for Sudoku. The algorithm effectiveness is verified with images taken from cameras. In this paper, a pixel to pixel comparison or a three layer Neural Network is used to recognize digits from 1 to 9 in Sudoku puzzles.
{"title":"A novel and automatic character extraction and recognition for Sudoku puzzle solving","authors":"Tanh Minh Ly, D. Vo","doi":"10.1109/ATC.2015.7388388","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388388","url":null,"abstract":"This paper proposes a novel algorithm to automatically solve a Sudoku puzzle on images taken from magazines or computer game software. The process involves preprocessing the image, extracting characters, recognizing characters and solving puzzle, which all are specifically designed for Sudoku. The algorithm effectiveness is verified with images taken from cameras. In this paper, a pixel to pixel comparison or a three layer Neural Network is used to recognize digits from 1 to 9 in Sudoku puzzles.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/ATC.2015.7388338
Tran Van Long
High-dimensional data visualization is a changing task with many applications in a various fields of sciences. Parallel coordinates is one of the most widely used information visualization technique for multivariate data analysis and high-dimensional geometry. The dimension ordering is an original problem for exploring structures in a high-dimensional data space. In this paper, we propose a new metric for measuring distance between two line-segment on the parallel coordinates. The metric is suitable and effective on the parallel coordinates. We use our metric distance for finding an optimal dimension ordering on the parallel coordinates. Finally, we demonstrate our method can be applied to visualize clusters in high-dimensional data on the parallel coordinates.
{"title":"A new metric on parallel coordinates and its application for high-dimensional data visualization","authors":"Tran Van Long","doi":"10.1109/ATC.2015.7388338","DOIUrl":"https://doi.org/10.1109/ATC.2015.7388338","url":null,"abstract":"High-dimensional data visualization is a changing task with many applications in a various fields of sciences. Parallel coordinates is one of the most widely used information visualization technique for multivariate data analysis and high-dimensional geometry. The dimension ordering is an original problem for exploring structures in a high-dimensional data space. In this paper, we propose a new metric for measuring distance between two line-segment on the parallel coordinates. The metric is suitable and effective on the parallel coordinates. We use our metric distance for finding an optimal dimension ordering on the parallel coordinates. Finally, we demonstrate our method can be applied to visualize clusters in high-dimensional data on the parallel coordinates.","PeriodicalId":142783,"journal":{"name":"2015 International Conference on Advanced Technologies for Communications (ATC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121450474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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