Low power strategy about correlator array for CDMA baseband processor

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI:10.1109/SIPS.1999.822357

Chung-Wei Ku, Fu-Yen Kuo, Chi-Kuang Chen, Liang-Gee Chen

引用次数: 4

Abstract

This paper discusses the design, implementation, and performance evaluation of a low powered correlator architecture for multi-code CDMA systems. In CDMA systems, correlators are used to de-spread the received signals and are important blocks for RAKE receivers. We proposed a low powered correlator architecture to de-spread input with several PN sequence concurrently, According to our preliminary simulation results, the suggested architecture can de-spread the input signal with two PN codes simultaneously and save 41% power consumption compared with traditional correlator architecture.

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CDMA基带处理器相关器阵列的低功耗策略

本文讨论了一种适用于多码CDMA系统的低功耗相关器架构的设计、实现和性能评估。在CDMA系统中，相关器用于接收信号的消散，是RAKE接收机的重要模块。提出了一种具有多个PN序列的低功耗相关器结构，初步仿真结果表明，该结构可以同时对两个PN序列的输入信号进行解扩，与传统相关器结构相比，功耗节省41%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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