Body-bootstrapped-buffer circuit for CMOS static power reduction

Abstract

In this paper, we present a new CMOS circuit design for increasing the threshold voltages (VT) of MOSFETS to reduce power consumption. Using a single voltage source VDD, the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise VT. Consequentially, static power consumption is reduced. The circuit is integrated into a 256-bit Ripple Carry Adder and a 32-bit Braun multiplier. Simulation results based on Chartered Semiconductor Manufacturing Private Limitedpsilas (CHRT) 0.25-mum, 0.18-mum and Berkeley Predictive Technology Modelpsilas (BPTM) 90-nm processes showed good trade-offs between power savings and delay.