A fully automated large-scale addressable test chip design with high reliability

Bo Zhang, Weiwei Pan, Yongjun Zheng, Zheng Shi, Xiaolang Yan
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引用次数: 5

Abstract

During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper, we present a novel large-scale addressable test chip development procedure. Based on components for automation, this procedure is fully integrated and able to reduce layout time to 10% and eliminate much of the potential for human error. A 32×32 array on a 45nm technology has been designed and manufactured with this procedure; the silicon test data further prove the reliability and effectiveness of this procedure.
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具有高可靠性的全自动大规模可寻址测试芯片设计
在现代半导体工艺的发展过程中,其复杂性和自由度越来越高,需要大量不同的测试结构来测试和保证良率和可制造性。为了提高芯片面积的利用率,提出了测试芯片的寻址方法。本文提出了一种新的大规模可寻址测试芯片的开发方法。基于自动化组件,该流程是完全集成的,能够将布局时间减少到10%,并消除了大部分人为错误的可能性。使用此程序设计和制造了45纳米技术的32×32阵列;硅测试数据进一步证明了该方法的可靠性和有效性。
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