Designing variability tolerant logic using evolutionary algorithms

Abstract

This paper describes an approach to create novel, robust logic-circuit topologies, using several evolution-inspired techniques over a number of design stages. A library of 2-input logic gates are evolved and optimised for tolerance to the effects of intrinsic variability. Block-level designs are evolved using evolutionary methods (CGP). A method of selecting the optimal gates from the library to fit into the block-level designs to create variability-tolerant circuits is also proposed.