Challenges of low power SRAM design in Nanoscale Era

Abstract

Technology advancement demands more functionality per device with reducing device dimensions as a result of technology scaling. SRAM represents the technology workhorse due to its compatibility with the logic. The denser SRAM is the requirement for modern high performance. The stability of SRAM in low power regime needs attention due to increasing effects of process variations. These variations are dominant for the scaled devices. Therefore, the reliability of the overall SoC is mostly affected by the reliability of the SRAM. In this paper, the challenges to low-power SRAM design, based on the scaling, power dissipation, and process variations are discussed. The result of the discussion is that the challenges for SRAM designing increase with technology scaling.