Analysis of a novel Elevated Source Drain MOSFET with reduced Gate-Induced Drain-Leakage current

Abstract

A new self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. Proposed ESD structure is characterized by sidewall spacer width (W/sub S/) and recessed-channel depth (X/sub R/) which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. The GIDL current in the proposed ESD structure is reduced as the region with the peak electric field is shifted toward the drain side.