GaAs Schmitt trigger memory cell design

Abstract

A GaAs five-transistor static memory cell is proposed. It is derived from nMOS Schmitt trigger. The memory cell overcomes the subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small design area and allows large memory arrays to be realized. A prototype was implemented in a 1 /spl mu/m non-self aligned GaAs MESFET technology with read and write access time of 1.0 ns and 1.25 ns, respectively.<>