A vector DSP for imaging

Abstract

The CW4011 is an SoC containing a DSP with a novel vector architecture. It exploits the parallelism and narrow data typical of image processing to gain high performance at a low cost and power. It contains eight 32-bit datapaths all working off of a single instruction. It can do 16 16-bit MACs/cycle, and also four 32-bit memory accesses per cycle to 128 KB of on-chip memory. It also contains a serial datapath for handling low-performance code and OS functions. The chip also includes memory, video, and IO interfaces on an industry-standard bus. it is built in 0.18 /spl mu/m CMOS technology, is 7.8 /spl times/ 6.8 mm, runs at 200 MHz (worst-case) and draws less than 500 mW. This gives the best cost-performance of any processor on the market for imaging applications.