J. Abella, C. Bulla, Guillem Cabo, F. Cazorla, A. Cristal, Max Doblas, R. Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, R. Martínez, J. Mendoza, F. Moll, Miquel Moreteó, Julian Pavon, Cristóbal Ramíez, M. A. Ramírez, Carlos Rojas, A. Rubio, Abraham Ruiz, Nehir Sonmez, Víctor Soria, L. Terés, O. Unsal, M. Valero, Iván Vargas, L. Villa
{"title":"An Academic RISC-V Silicon Implementation Based on Open-Source Components","authors":"J. Abella, C. Bulla, Guillem Cabo, F. Cazorla, A. Cristal, Max Doblas, R. Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, R. Martínez, J. Mendoza, F. Moll, Miquel Moreteó, Julian Pavon, Cristóbal Ramíez, M. A. Ramírez, Carlos Rojas, A. Rubio, Abraham Ruiz, Nehir Sonmez, Víctor Soria, L. Terés, O. Unsal, M. Valero, Iván Vargas, L. Villa","doi":"10.1109/DCIS51330.2020.9268664","DOIUrl":null,"url":null,"abstract":"The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V processor designed and fabricated by a Spanish or Mexican academic institution, and will be the basis of future RISC-V designs jointly developed by these institutions. This paper summarizes the design tasks, for FPGA first and for SoC later, from high architectural level descriptions down to RTL and then going through logic synthesis and physical design to get the layout ready for its final tapeout in CMOS 65nm technology.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"31 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS51330.2020.9268664","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V processor designed and fabricated by a Spanish or Mexican academic institution, and will be the basis of future RISC-V designs jointly developed by these institutions. This paper summarizes the design tasks, for FPGA first and for SoC later, from high architectural level descriptions down to RTL and then going through logic synthesis and physical design to get the layout ready for its final tapeout in CMOS 65nm technology.