An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2016-11-01 DOI:10.1109/ASSCC.2016.7844141

Xuqiang Zheng, Chun Zhang, S. Yuan, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang

引用次数: 4

Abstract

An improved clock data recovery (CDR) operating at 40 Gb/s is implemented in 65 nm CMOS technology. Passive low-pass filters (LPFs) with adaptively adjusted bandwidth are introduced into the data-sampling path to automatically balance jitter tracking and jitter suppression for data decisions. Additionally, a time-averaging based compensating phase interpolator (PI) is proposed to not only improve the phase-step uniformity but also reduce phase-spacing drifting between edge and data sampling clocks. Measurement results show that different bandwidths for jitter transfer (4 MHz) and jitter tolerance (20 MHz) can be obtained. The total jitter of recovered clocks for edge-sampling and data-sampling are 11.48 ps and 7.66 ps, respectively. Meanwhile, the introduced jitter-suppression filters improve the maximum tolerable amplitude of sinusoidal jitter from 0.31 UI to 0.41 UI at 100 MHz.

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带有抖动抑制滤波器和相位补偿插值器的改进的40gb /s CDR

采用65nm CMOS技术实现了40gb /s的时钟数据恢复(CDR)。在数据采样路径中引入带宽自适应调节的无源低通滤波器(lpf)，自动平衡抖动跟踪和抖动抑制对数据决策的影响。此外，提出了一种基于时间平均的补偿相位插补器(PI)，不仅提高了相步均匀性，而且减少了边缘时钟和数据采样时钟之间的相间距漂移。测量结果表明，可以获得不同的抖动传输带宽(4 MHz)和抖动容差(20 MHz)。边缘采样和数据采样恢复时钟的总抖动分别为11.48 ps和7.66 ps。同时，引入的抖动抑制滤波器在100 MHz时将正弦抖动的最大容忍幅度从0.31 UI提高到0.41 UI。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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