Efficient high-speed CIC decimation filter

Abstract

This paper presents an efficient architecture for the first carry-save integrator stage in a high-speed cascaded integrator-comb (CIC) decimation filter based on exploiting the carry propagation properties in a carry-save accumulator. The architecture can reduce the number of registers (by 6.3% to 13.5% in our examples) and replace a large number of full-adders by half-adders (18% to 42% in our examples), thus saving area and power. Significant savings are achieved when the decimation rate is high and the number of integrator stages is small.