Heirarchical Full-Chip Fast-Simulation Based Design Mitigation of CHC in NAND Flash Memory

Abstract

Industry-standard Circuit Reliability simulation Tools (ICRT) to simulate Channel Hot Carrier (CHC) is either not possible at the full-chip level consisting of few million transistors or time consuming and prone to abrupt termination of simulation due to resource usage anomalies at reasonable large sub-block level. We have proposed a hierarchical design-in-reliability methodology to identify CHC aging of critical transistors accurately at full-chip level in 10x faster time than required by ICRT. Accurate reliability simulation and design mitigation is later carried out at much smaller and critical sub-block level using ICRT. We have demonstrated our methodology in screening critical blocks in a NAND flash memory and the results are provided thus enabling reliable and faster time to tape-out.