Yohan Kim, U. Monga, Jungmin Lee, Minkyoung Kim, Jaesung Park, C. Yoo, Kyungjin Jung, Sungduk Hong, Sung Jin Kim, D. Kim, Hokyu Kang
{"title":"The efficient DTCO Compact Modeling Solutions to Improve MHC and Reduce TAT","authors":"Yohan Kim, U. Monga, Jungmin Lee, Minkyoung Kim, Jaesung Park, C. Yoo, Kyungjin Jung, Sungduk Hong, Sung Jin Kim, D. Kim, Hokyu Kang","doi":"10.1109/SISPAD.2018.8551725","DOIUrl":null,"url":null,"abstract":"This paper introduces the recent modeling challenges of the Process Development Kit (PDK) development due to the limitations of transistor scaling and the impact of new process technologies. And a new modeling solution, Agile PDK is presented to break though these development challenges by enabling the Design Technology Co-Optimization (DTCO) activities in the manufacturing levels. A series of advanced algorithms are newly introduced to not only reduce the PDK development time (TAT), but also improve the model accuracies and Model-to-Hardware Correlation (MHC). It is applied to the latest DRAM technology and dramatically reduces the development TAT up to 50% with improved model accuracies.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2018.8551725","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper introduces the recent modeling challenges of the Process Development Kit (PDK) development due to the limitations of transistor scaling and the impact of new process technologies. And a new modeling solution, Agile PDK is presented to break though these development challenges by enabling the Design Technology Co-Optimization (DTCO) activities in the manufacturing levels. A series of advanced algorithms are newly introduced to not only reduce the PDK development time (TAT), but also improve the model accuracies and Model-to-Hardware Correlation (MHC). It is applied to the latest DRAM technology and dramatically reduces the development TAT up to 50% with improved model accuracies.