A 90 nm 1 GHz 22 mW 16/spl times/16-bit 2's complement multiplier for wireless baseband

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221212

B. Zeydel, V. Oklobdzija, S. Mathew, R. Krishnamurthy, S. Borkar

引用次数: 9

Abstract

This paper describes a static 16/spl times/16-bit 2's complement wireless baseband multiplier testchip in 1.2 V, 90 nm dual-Vt CMOS technology. One-hot Booth encoding, sum/delay difference optimized 3:2 compressor tree, and signal-profile optimized final adder schemes are employed to achieve 1 GHz, 22 mW operation at 1.2 V, scalable to 500 MHz, 3 mW at 0.8 V.

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用于无线基带的90 nm 1 GHz 22 mW 16/spl倍/16位2的补码乘法器

本文介绍了一种采用1.2 V、90nm双vt CMOS技术的静态16/spl倍/16位2补码无线基带乘法器测试芯片。采用单热室编码，sum/delay difference优化的3:2压缩器树，以及信号轮廓优化的最终加法器方案，可实现1.2 V下1 GHz, 22 mW的工作，可扩展到500 MHz, 0.8 V下3 mW的工作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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