Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology

Abstract

Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner.