{"title":"Implementation Of Bayesian Network In FPGA Circuit","authors":"Z. Kulesza, W. Tylman","doi":"10.1109/MIXDES.2006.1706677","DOIUrl":null,"url":null,"abstract":"The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2006.1706677","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted
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