A high performance VLSI architecture for Fast Two-Step Search algorithm for sub-pixel motion estimation

Abstract

This paper proposes a parallel architecture for Fast Two-Step Search algorithm, which is used in sub-pixel motion estimation with reduced complexity. As frequent data access is necessary to execute the algorithm which involves interpolation, an architecture efficient in terms of the memory bandwidth is suitable for implementing the algorithm. In the present paper, an architecture based on an intelligent memory configuration has been proposed for the implementation of Fast Two-Step Search algorithm for half-pixel motion estimation. The proposed architecture is based upon nine processing elements (PEs) accompanied with the use of intelligent data arrangement and memory configuration. The proposed architecture is designed to be used as part of H.264 video coding. The architecture, which has been synthesized under Synopsys Design Vision environment, can work at a frequency up to 90 MHz while consuming a power of approximately 459 mW. The proposed architecture provides the solution for realtime low bit rate video applications.