{"title":"Area Efficient Low-Power Static Explicit-Pulsed Flip-Flop with Local Feedback","authors":"K. Yeo, W. Goh, M. Phyu","doi":"10.1109/EDSSC.2005.1635381","DOIUrl":null,"url":null,"abstract":"In this paper, a static explicit-pulsed single/double edge-triggered flip-flop suitable for low-power application is presented. It offers energy savings by reduction unnecessary internal switching activities. All circuits are simulated in 0.18-μm CMOS technology with a supply voltage of 1.8V. The developed circuit provides up to 18.1% total gate-area reduction and also 19.4% improvement in the power-delay over the best performing flip-flop reported to-date.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2005.1635381","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a static explicit-pulsed single/double edge-triggered flip-flop suitable for low-power application is presented. It offers energy savings by reduction unnecessary internal switching activities. All circuits are simulated in 0.18-μm CMOS technology with a supply voltage of 1.8V. The developed circuit provides up to 18.1% total gate-area reduction and also 19.4% improvement in the power-delay over the best performing flip-flop reported to-date.
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