H. Okano, A. Suga, T. Shiota, Y. Takebe, Yasuki Nakamura, N. Higaki, Haruo Kimura, H. Miyake, T. Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, Mitsuru Sasaki, Naruyoshi Ando, Tomohiro Yamana, I. Fukushi, S. Tago, F. Hayakawa, Teruhiko Kamigata, S. Imai, Atsushi Satoh, Yasuaki Hatta, Noboru Nishimura, Y. Asada, Taizo Satoh, Takao Sukemura, S. Ando, Hiromasa Takahashi
{"title":"An 8-way VLIW embedded multimedia processor built in 7-layer metal 0.11 /spl mu/m CMOS technology","authors":"H. Okano, A. Suga, T. Shiota, Y. Takebe, Yasuki Nakamura, N. Higaki, Haruo Kimura, H. Miyake, T. Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, Mitsuru Sasaki, Naruyoshi Ando, Tomohiro Yamana, I. Fukushi, S. Tago, F. Hayakawa, Teruhiko Kamigata, S. Imai, Atsushi Satoh, Yasuaki Hatta, Noboru Nishimura, Y. Asada, Taizo Satoh, Takao Sukemura, S. Ando, Hiromasa Takahashi","doi":"10.1109/ISSCC.2002.992265","DOIUrl":null,"url":null,"abstract":"A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992265","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.
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