{"title":"A 13T radiation hardened SRAM bitcell for low-voltage operation","authors":"L. Atias, A. Teman, A. Fish","doi":"10.1109/S3S.2013.6716579","DOIUrl":null,"url":null,"abstract":"In this work, a radiation hardened low-voltage memory cell for ultra-low power operation is proposed. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2013.6716579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this work, a radiation hardened low-voltage memory cell for ultra-low power operation is proposed. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism.
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