Guided gate-level ATPG for sequential circuits using a high-level test generation approach

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI:10.1109/ASPDAC.2010.5419843

B. Alizadeh, M. Fujita

引用次数: 13

Abstract

This paper proposes a non-scan gate-level Automatic Test Pattern Generation (ATPG) methodology which keeps the regularity in the arithmetic operations while reasoning about these operations for generating high-level test patterns from only faulty behavior of the design. Then by considering generated high-level test patterns as constraints and passing them to a SMT-solver we are able to automatically and efficiently generate gate-level test patterns. Experimental results show robustness and reliability of our method compared to other contemporary methods in terms of the fault coverage and CPU time.

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使用高级测试生成方法的顺序电路引导门级ATPG

本文提出了一种非扫描门级自动测试模式生成(ATPG)方法，该方法在保持算术运算的规律性的同时对这些运算进行推理，从而仅从设计的错误行为生成高级测试模式。然后，通过考虑将生成的高级测试模式作为约束并将它们传递给smt求解器，我们能够自动且有效地生成门级测试模式。实验结果表明，在故障覆盖率和CPU时间方面，该方法与现有方法相比具有较好的鲁棒性和可靠性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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