Environmental Performance of Sealed Chip-On-Board (scob) Memory Circuits

Abstract

This report presents the results of environmental testing of sealed chip-on-board (SCOB) memory circuits. Samples consisted of four SRAM chips mounted on fine line PWBs (MCM-L technology). A complete design of experiments (DOE) matrix included two PWB sources, three die attachment adhesives, one moisture passivation coating (plasma enhanced, chemical vapor deposited silicon nitride), and two encapsulants (a silicone gel and an epoxy glob-top material). DOE was also employed to set up the environmental test scheme using tests selected from MIL-STD-883, and HAST. A set of conventional thin film hybrid circuit samples packaged in hermetic ceramic packages was included in the environmental test scheme as a control. Failure analyses of test samples and conclusions on performance of adhesives and protective coatings are presented.