{"title":"Core-based Design Of Systems On A Chip","authors":"J. Henkel, F. Vahid","doi":"10.1109/ASIC.1998.723087","DOIUrl":null,"url":null,"abstract":"The growth in integration capacity allows to integrate complete systems on one single chip (SOC: systems-on-a-chip). Since traditional design tools can not keep pace with this rapid growth, so-called core-based design methodologies become more and more important for today’s system designer. In this context, a core can be a microprocessor, a controller, a multimedia application, etc. Distinguished are often three levels of cores: soft, firm and hard cores. Whereas a soft core is a non-synthesized, often technology independent HDL description of a circuit, a hard core is readily synthesized and verified. A f i core is somewhere between and owns some peculiarities of soft cores and some of hard cores. By composing a system of a mixture of soft, f i and hard cores, the system designer is enabled to achieve the best compromise between parameterization, customization and re-usability. As a result, the time-to-market as well as system costs can be drastically reduced. In this four-hour tutorial the authors will give an overview of core-based design methodologies while mainly focussing on the following decisive design aspects: Integration of cores on a chip: a) Integration is the process of adapting various cores to each other according to given design goals and afterwards synthesizing these cores (if applicable) in order to obtain a singlechip-solution. Among other steps, this procedure involves the selection of appropriate interfaces since this matter is directly related to design goalslconstraints like system performance, total chip area, system power dissipation, system costs, etc. Whereas intra-chip interfaces (between the SOC and the environment, for example), is limited to standard interfaces. The tutorial will give some examples for the integration procedure with emphasize on interface selection for different design goalskonstraints. Frank Vahid Department of Computer Science University of Califbrnia Riverside Riverside, California 9252 1-0304, USA vahid(ii,cs.ucr.edu","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.723087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The growth in integration capacity allows to integrate complete systems on one single chip (SOC: systems-on-a-chip). Since traditional design tools can not keep pace with this rapid growth, so-called core-based design methodologies become more and more important for today’s system designer. In this context, a core can be a microprocessor, a controller, a multimedia application, etc. Distinguished are often three levels of cores: soft, firm and hard cores. Whereas a soft core is a non-synthesized, often technology independent HDL description of a circuit, a hard core is readily synthesized and verified. A f i core is somewhere between and owns some peculiarities of soft cores and some of hard cores. By composing a system of a mixture of soft, f i and hard cores, the system designer is enabled to achieve the best compromise between parameterization, customization and re-usability. As a result, the time-to-market as well as system costs can be drastically reduced. In this four-hour tutorial the authors will give an overview of core-based design methodologies while mainly focussing on the following decisive design aspects: Integration of cores on a chip: a) Integration is the process of adapting various cores to each other according to given design goals and afterwards synthesizing these cores (if applicable) in order to obtain a singlechip-solution. Among other steps, this procedure involves the selection of appropriate interfaces since this matter is directly related to design goalslconstraints like system performance, total chip area, system power dissipation, system costs, etc. Whereas intra-chip interfaces (between the SOC and the environment, for example), is limited to standard interfaces. The tutorial will give some examples for the integration procedure with emphasize on interface selection for different design goalskonstraints. Frank Vahid Department of Computer Science University of Califbrnia Riverside Riverside, California 9252 1-0304, USA vahid(ii,cs.ucr.edu