A 138 dB dynamic range CMOS image sensor with new pixel architecture

D. Stoppa, A. Simoni, L. Gonzo, M. Gottardi, G. Dalla Betta
{"title":"A 138 dB dynamic range CMOS image sensor with new pixel architecture","authors":"D. Stoppa, A. Simoni, L. Gonzo, M. Gottardi, G. Dalla Betta","doi":"10.1109/ISSCC.2002.992928","DOIUrl":null,"url":null,"abstract":"A 128/spl times/64 pixel image sensor in 0.35 /spl mu/m 3.3V CMOS technology achieves 138 dB dynamic range by adapting single-pixel integration time to the local illumination conditions. Video frame rate is achieved with 0.2% rms temporal noise and 14 mW power in a test chip.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992928","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14

Abstract

A 128/spl times/64 pixel image sensor in 0.35 /spl mu/m 3.3V CMOS technology achieves 138 dB dynamic range by adapting single-pixel integration time to the local illumination conditions. Video frame rate is achieved with 0.2% rms temporal noise and 14 mW power in a test chip.
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一种具有新像素结构的138 dB动态范围CMOS图像传感器
采用0.35 /spl mu/m 3.3V CMOS技术的128/spl倍/64像素图像传感器通过调整单像素集成时间来适应局部照明条件,实现了138 dB的动态范围。在测试芯片中,视频帧率以rms为0.2%的时间噪声和14mw的功率实现。
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